Having major problems with this problem:
Design a sub system that serially transfers data between two 8 bit registers and maintains a copy of the transferred data in the original register.
1. The register consists of 8 Flip-Flops each having the ability to hold 1 bit of the 8 bits.
2. Inputs to the register includes:
i) Inputs to the flip-flops, ii) a clock signal, iii) a signal to control the transfer and any other signal you might need to accomplish the task
*Note: that register A needs feedback to maintain a copy of the transferred data.
Lastly, need to design some logic circuit to accomplish the transfer, i.e., circuitry that provides a transfer control signal.
Could you please draw the logic gates and indicate if you're using a D, S-R, J-K or any other Flip-Flops. Indicate the State Table (include any additional input signals used e.g., clear, enable, or preset signals.
Any timing diagram showing the signals would be great
Thanks for any help on this
Design a sub system that serially transfers data between two 8 bit registers and maintains a copy of the transferred data in the original register.
1. The register consists of 8 Flip-Flops each having the ability to hold 1 bit of the 8 bits.
2. Inputs to the register includes:
i) Inputs to the flip-flops, ii) a clock signal, iii) a signal to control the transfer and any other signal you might need to accomplish the task
*Note: that register A needs feedback to maintain a copy of the transferred data.
Lastly, need to design some logic circuit to accomplish the transfer, i.e., circuitry that provides a transfer control signal.
Could you please draw the logic gates and indicate if you're using a D, S-R, J-K or any other Flip-Flops. Indicate the State Table (include any additional input signals used e.g., clear, enable, or preset signals.
Any timing diagram showing the signals would be great
Thanks for any help on this
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I,
I'm going to give this a whack, but I don't plan to draw a logic diagram or circuit, because it sounds painfully simple to me.
First you so correctly observe that:
"...register A needs feedback to maintain a copy of the transferred data". This would be from Q8 back to D1. [D FlipFlops]
OK, so you have an 8 bit shift register (A) where the data simply circulates and winds up where it started after 8 clock pulses. With "D" F-Fs this is simple.
Now, to shift it's contents into the other "B" register, it must also be the same type of shift register with it's input (D9) coming from the output of register"A" (Q8).
THEREFORE this makes one 16 bit shift register (Q1-Q16) with:
Q1 going to D2,
Q2 going to D3
Q3 going to D4
....
Q15 going to D16
Now the output of the 8th bit (Q8 now in the center) going back to the "D1" input (of "A").
I'm going to give this a whack, but I don't plan to draw a logic diagram or circuit, because it sounds painfully simple to me.
First you so correctly observe that:
"...register A needs feedback to maintain a copy of the transferred data". This would be from Q8 back to D1. [D FlipFlops]
OK, so you have an 8 bit shift register (A) where the data simply circulates and winds up where it started after 8 clock pulses. With "D" F-Fs this is simple.
Now, to shift it's contents into the other "B" register, it must also be the same type of shift register with it's input (D9) coming from the output of register"A" (Q8).
THEREFORE this makes one 16 bit shift register (Q1-Q16) with:
Q1 going to D2,
Q2 going to D3
Q3 going to D4
....
Q15 going to D16
Now the output of the 8th bit (Q8 now in the center) going back to the "D1" input (of "A").
12
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